Nonvolatile memory devices may have various structural designs. FIG. 1 depicts an example of a nonvolatile memory cell 10 that is implemented in and on a substrate 8. Memory cell 10 comprises source and drain regions 22, 24 and a channel 12 disposed between the source and drain regions 22, 24. Overlying the channel 12 is a charge-trapping structure 11, which may include a charge-trapping nitride layer 16 (e.g., silicon nitride) disposed between two oxide layers 14, 18 (e.g., silicon oxide). Each memory cell 10 further comprises a gate electrode 20 that overlies the charge-trapping structure 11, and the source and drain regions 22, 24 each have a corresponding electrode, as shown in FIG. 1. By properly manipulating the relative voltages among the substrate 8, the source and drain regions 22, 24 and the gate 20, it is possible to separately erase, store (or program) and read two bits of information (a right bit and a left bit) in each memory cell 10.
However, conventional flash memory cells may have several possible concerns depending on their designs, dimensions, and operating voltages. For example, problems such as lateral charge transportation in the storage element, low-Vt state threshold voltage instability, high-Vt state charge loss, and a second bit effect (cross-talk) and/or a short channel effect may occur. In some cases, lateral charge transportation in the storage element, such as the charge-trapping layer 16 may occur from the left bit to the right bit if the isolation between the two bits is insufficient. For devices having smaller dimensions, short channel effect represents the undesirable effect from the gradual shorting together of the source and drain regions 22, 24 as the gate and channel length shortens.
Another possible problem is the second bit effect. The second-bit effect may be generated during a forward reading when one bit of data is already stored in the trapping layer at one side, such as the side of the drain region. Particularly, the bit of information that is already stored at one side may affect a threshold voltage of the other bit in reverse read and vice versa. Therefore, there is a need to improve the design of memory devices to mitigate or avoid one or more of the aforementioned problems of the conventional devices.